Niagara2
From View
[ Chip Multi Processor Watch ]
Contents |
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Purpose and Target Market
General Purpose Server (and HPC?) processor.
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Architecture
8x UltraSPARC cores. Each core has two thead engines, each one capable of running four threads.
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Interconnect and Topologies
Buses?
Full Crossbar with 8 data destinations, the 8 cores, and 9 data sources, the eight L2 cache banks and I/O (PCI Express and the two 10Gbps controllers).
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Memory Structure and Hierarchy
- Shared memory architecture
- 16 KB L1I-cache (8 way)
- 8 KB L1D-cache (4 way)
- 4 MB shared L2 cache in eight banks. Each two banks are associated with a dual-channel FBDIMM memory controller.
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Special Purpose Hardware Units
- One FPU per core (instead of one chip in T1), shared between the 9 threads. The FPUs suppert Sun’s VIS 2.0 SIMD extensions and are fully pipelined, except for square root and divide.
- One encryption engines per core.
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I/O and Peripherals
DMA engines? Hypertransport?
- 4x dual-channel FBDIMM memory controllers
- 2x 10Gbps Ethernet (XAUI) ports with packet classification and filtering
- 8x encryption engines (instead of just one in T1) with DMA engines.
- 1x PCI Express x8 port
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Physical Properties
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Process Technology
which year? Fast or slow process? multi-Vt process?
- 65 nm fab. process
- 11 metal layers
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Die Size
relative size of logic vs arrays? relative sizes of cores and others?
Dia size: 342 mm^2
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Power Dissipation
Joules per SPEC?
Worst case power usage: 84W
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Usage Model
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Program Model
Assembly? C/C++? Domain specific design language?
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Software Development Environment
System design tool stack? Availability of layers in this tool stack?
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Recent News and Publications
Product annoucements? Roadmaps? Industry comments? Any other references?
