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From View
[ Chip Multi Processor Watch ]
Contents |
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Purpose and Target Market
General purpose Server/Workstation/Desktop Processor.
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Architecture
4 homogeneous next generation Opteron x86_64 cores.
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Interconnect and Topologies
The chip has a crossbar switch between the shared L2 cache and the memory controllers and HyperTransport links.
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Memory Structure and Hierarchy
Shared memory? Distributed memory?
- 128 kB private L1 cache, split in 64 kB data and 64 kB instruction cache.
- 512 kB private L2 cache
- 2 MB shared L3 cache
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I/O and Peripherals
Each chip has the following peripherals:
- 2 64-bit DDR2 memory controllers (in stead of one 128 bits memory controller in K8)
- 4 16-bit HyperTransport 3.0 lanes (3 for fully interconnected 4-way SMP and 1 to I/O) that can be split in in 8 8-bit lanes for fully interconnected 8-way SMP plus I/O access to each chip. HyperTransport speed will be initially 2.0 GT/s and in future may operate a 5.2 GT/s.
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Physical Properties
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Process Technology
Whose fab? which year? Fast or slow process? multi-Vt process?
11 metal layers
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Die Size
Relative size of logic vs arrays? relative sizes of cores and others?
Die size: 291 mm^2
- L3: ~20% of die area
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Power Dissipation
Average or peak Watts? Joules per SPEC?
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Usage Model
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Program Model
Common programing languages for x86:
- x86 Assembler
- C/C++
- Java
- C#
...
Common parallel programming models for x86:
- Pthreads
- OpenMP
- MPI
- MapReduce
...
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Software Development Environment
System design tool stack? Availability of layers in this tool stack?
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