IXP1200

From View

Contents 1 Number of Processors 2 Basic Processing Element(s) 3 Interconnect and Topologies 4 Memory Structure and Hierarchy 5 Special Purpose Hardware Units 6 I/O and Peripherals 7 Process Technology 8 Die Size 9 Power Dissipation 10 Program Model 11 Software Development Environment

Number of Processors

6 Microengines 1 StrongArm

Basic Processing Element(s)

Microengines - 5 stage RISC cores with instruction sets tuned for packet processing

Interconnect and Topologies

Memory Structure and Hierarchy

Special Purpose Hardware Units

I/O and Peripherals

Process Technology

Die Size

Power Dissipation

Program Model

Software Development Environment