SiCortex Unveils
Posted by Bryan Catanzaro on November 10, 2006
SiCortex went public this week with its custom MIPS HPC cluster-in-a-cabinet. I couldn't help but smile when I read this line from one of their white papers: "Contrary to conventional wisdom, high performance computers must dramatically reduce their power consumption in order to achieve their performance goals." Sound familiar? =)
SiCortex views parallel computing as primarily a data movement problem, so they chose simple, in order MIPS cores to reduce power consumption, allowing them to pack the processors very densely. They fit 6 MIPS cores & their caches, memory controllers, PCI Express controllers, and Fabric ports on each chip, then tile 27 of these chips along with their DDR2 memories onto each blade. Their high end machine has 36 blades, for a total of almost 6000 cores, consuming only 18 kW. Their low power consumption allows them to pack the chips very densely physically, which along with an interesting network topology, allows interprocessor communications to be very economical - at max only 6 hops, whereas a 3D torus interconnect would require 15.
SiCortex envisions MPI as the programming model of choice.
This product is some additional anecdotal evidence in support of our position that small, simple processors are the way to go.
Some links:
SiCortex views parallel computing as primarily a data movement problem, so they chose simple, in order MIPS cores to reduce power consumption, allowing them to pack the processors very densely. They fit 6 MIPS cores & their caches, memory controllers, PCI Express controllers, and Fabric ports on each chip, then tile 27 of these chips along with their DDR2 memories onto each blade. Their high end machine has 36 blades, for a total of almost 6000 cores, consuming only 18 kW. Their low power consumption allows them to pack the chips very densely physically, which along with an interesting network topology, allows interprocessor communications to be very economical - at max only 6 hops, whereas a 3D torus interconnect would require 15.
SiCortex envisions MPI as the programming model of choice.
This product is some additional anecdotal evidence in support of our position that small, simple processors are the way to go.
Some links: